Titre:	A manycore vision processor for real-time smart cameras
Auteur(s):	Silva, Bruno Almeida da Lima, Arthur Mendes Arias Garcia, Janier Huebner, Michael Silva, Jones Yudi Mori Alves da
metadata.dc.identifier.orcid:	https://orcid.org/ 0000-0001-5203-3048 https://orcid.org/ 0000-0002-1790-3869 https://orcid.org/ 0000-0001-6707-853X
Assunto::	Multiprocessadores em chip Processamento de imagens Visão por computador Câmera inteligente
Date de publication:	27-oct-2021
Editeur:	MDPI
Référence bibliographique:	SILVA, Bruno A. da et al. A manycore vision processor for real-time smart cameras. Sensors, v. 21, n. 21, 7137, 2021. DOI: https://doi.org/10.3390/s21217137. Disponível em: https://www.mdpi.com/1424-8220/21/21/7137. Acesso em: 1 nov. 2021.
Abstract:	Real-time image processing and computer vision systems are now in the mainstream of technologies enabling applications for cyber-physical systems, Internet of Things, augmented reality, and Industry 4.0. These applications bring the need for Smart Cameras for local real-time processing of images and videos. However, the massive amount of data to be processed within short deadlines cannot be handled by most commercial cameras. In this work, we show the design and implementation of a manycore vision processor architecture to be used in Smart Cameras. With massive parallelism exploration and application-specific characteristics, our architecture is composed of distributed processing elements and memories connected through a Network-on-Chip. The architecture was implemented as an FPGA overlay, focusing on optimized hardware utilization. The parameterized architecture was characterized by its hardware occupation, maximum operating frequency, and processing frame rate. Different configurations ranging from one to eighty-one processing elements were implemented and compared to several works from the literature. Using a System-on-Chip composed of an FPGA integrated into a general-purpose processor, we showcase the flexibility and efficiency of the hardware/software architecture. The results show that the proposed architecture successfully allies programmability and performance, being a suitable alternative for future Smart Cameras.
Description:	This paper is an extended version of our paper published in —X Braziliam Symposium on Computing Systems Engineering—https://doi.org/10.1109/SBESC51047.2020.9277867.
Licença::	Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).
DOI:	https://doi.org/10.3390/s21217137
Collection(s) :	Artigos publicados em periódicos e afins

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